Sunday, December 23, 2012
Sunday, October 5, 2008
IC Custom Layout Design
IC Custom Layout Design
Integrated circuit layout, also known IC layout, IC mask layout, or mask design, is the representation of an integrated circuit in terms of planar geometric shapes which correspond to the patterns of metal, oxide, or semiconductor layers that make up the components of the integrated circuit.
Some of the layout considerations are given below,
(1) Contacts:
The source diffusion and the drain diffusion should be filled with the maximum number of contacts to reduce the resistance of the connection from the metal to the diffusion, and to maximize the amount of current that can flow through the contacts.
(2) Fingering:
Putting together transistors with fixed aspect ratio will not result in a compact layout. Fortunately, the aspect ratio of the transistor can be modified by using the transistor current equation. For example, the transistor with a width of 20um and a length of 0.2um is similar to having four transistors connected in parallel, each with a width of 5um and a length of 0.2um. The MOS is said to have 4 fingers.
(3) Manufacturing limitations:
Layout cannot be fabricated exactly as drawn in the layout due to the limitations in the manufacturing process, such as process tolerances and mask misalignment. Some of the manufacturing limitations are captured in the Spice transistor model. Two of the main parameters in the Spice transistor model are DW and DL. DW shows the delta difference of drawn W from effective W. DL shows the delta difference of drawn L from effective L.
(4) Speed of the transistor:
To increase the speed of the MOS, parasitic capacitance as well as resistance should be reduced. The frequency response of the transistor can be improved if the source capacitance and drain capacitance are reduced. The fingering technique allows the designer to reduce the drain and source area and in turn to reduce the parasitic capacitance.
Folded transistors also reduce the gate resistance. Resistivity of the poly is a few orders higher than the resistivity of the metal. The parasitic capacitances between the poly and the substrate, and between the metal and the poly, are very much larger than the parasitic capacitance between the metal to the substrate. Hence, using poly for interconnect could degrade the frequency response of the transistor if the poly routing is not optimized carefully.
(5) Protect the Gate:
The gate oxide underneath the poly is incredibly thin. If the charges accumulated on the poly is sufficiently large, the charges accumulated can damage the gate oxide. This is known as process antenna effect. The maximum amount of charges that can be accumulated on the poly is proportional to the area of the poly. Thus, an effective layout practice to prevent process antenna violation is to stay within the antenna ratio design rule of the respective technology. Some general guidelines are,
1)Minimize the use of poly for routing
2)Minimize the use of poly to connect the gates together
3)Do not place contact and via directly on top of the transistor’s gate.
4)Avoid routing over the gates of critical transistors
5)Avoid routing over active areas of critical transistors.
(6) Contacts and Vias:
A high percentage of IC manufacturing defects is related to faulty contact and via. Instead of using single contacts or vias, using at least double contacts or double vias whenever possible reduces the possibility of defects.
(7) Metal coverage of contacts and vias:
Additional metal coverage on the contacts and the vias should be done if they are located at the end of the metal. A larger metal coverage reduce contact or via resistance variation and also reduce the chance of an open contact or open via.
(8) Spacing from poly to diffusion:
The performance of the circuit can be degraded due to an increase in the capacitive coupling between the poly and the diffusion, and a change in the length and width of the transistor. So the spacing from poly to diffusion should be according to the technology rules.
(9) Reduction of disturbances:
Analog design performances are sensitive to electrical disturbance. Disturbance in the substrate should be minimized as much as possible.
Two common types of substrate disturbance are
- Disturbance from minority carrier
Minority carriers are injected into the substrate from the source diffusions and the drain diffusions when the source potential or the drain potential of NMOS is below the substrate potential or the source potential or the drain potential of PMOS is above the N-well potential.
The drifting of the minority creates a potential difference or triggers a latch-up.
To reduce disturbances from minority carrier, guard ring around noisy transistors can be used. Guard ring considerations are as following,
(i) NMOS in the p-substrate with should be surrounded by N-well guard ring. N-well guard ring should be tied to VDD. The N-diffusions from the NMOS could inject stray electrons into the substrate. These stray electrons could be collected efficiently by the N-well guard ring that is biased to VDD to attract the electrons.
(ii) PMOS in the N-well should be surrounded with P-diffusion guard ring.
P-diffusion guard ring should be tied to ground. P-diffusions from the
PMOS inject stray holes into the N-well. These stray holes could be
collected efficiently by the P-diffusion guard ring that is biased to ground to attract the holes.
Ideally, the guard rings should be placed as closely to the likely noise sources as possible. The guard rings are also placed around the critical transistors to minimize stray electrons and stray holes from affecting the critical transistors.
Substrate coupling noise
To reduce substrate coupling noise, the guard ring may be used in the following configuration around critical transistors.
(i) Surround NMOS in the p-substrate with p-tap guard ring that is connected to ground.
(ii) Surround PMOS in the N-well with n-tap guard ring that is connected to VDD.
An important layout practice is to ensure that there is no (or very little) current flowing through any part of the guard ring. There are some disadvantages of the guard rings like, guard rings take up a lot of area and they also add capacitive load to the transistor. So, if the area in the design is of utmost importance, then guard rings should be avoided.
Integrated circuit layout, also known IC layout, IC mask layout, or mask design, is the representation of an integrated circuit in terms of planar geometric shapes which correspond to the patterns of metal, oxide, or semiconductor layers that make up the components of the integrated circuit.
Some of the layout considerations are given below,
(1) Contacts:
The source diffusion and the drain diffusion should be filled with the maximum number of contacts to reduce the resistance of the connection from the metal to the diffusion, and to maximize the amount of current that can flow through the contacts.
(2) Fingering:
Putting together transistors with fixed aspect ratio will not result in a compact layout. Fortunately, the aspect ratio of the transistor can be modified by using the transistor current equation. For example, the transistor with a width of 20um and a length of 0.2um is similar to having four transistors connected in parallel, each with a width of 5um and a length of 0.2um. The MOS is said to have 4 fingers.
(3) Manufacturing limitations:
Layout cannot be fabricated exactly as drawn in the layout due to the limitations in the manufacturing process, such as process tolerances and mask misalignment. Some of the manufacturing limitations are captured in the Spice transistor model. Two of the main parameters in the Spice transistor model are DW and DL. DW shows the delta difference of drawn W from effective W. DL shows the delta difference of drawn L from effective L.
(4) Speed of the transistor:
To increase the speed of the MOS, parasitic capacitance as well as resistance should be reduced. The frequency response of the transistor can be improved if the source capacitance and drain capacitance are reduced. The fingering technique allows the designer to reduce the drain and source area and in turn to reduce the parasitic capacitance.
Folded transistors also reduce the gate resistance. Resistivity of the poly is a few orders higher than the resistivity of the metal. The parasitic capacitances between the poly and the substrate, and between the metal and the poly, are very much larger than the parasitic capacitance between the metal to the substrate. Hence, using poly for interconnect could degrade the frequency response of the transistor if the poly routing is not optimized carefully.
(5) Protect the Gate:
The gate oxide underneath the poly is incredibly thin. If the charges accumulated on the poly is sufficiently large, the charges accumulated can damage the gate oxide. This is known as process antenna effect. The maximum amount of charges that can be accumulated on the poly is proportional to the area of the poly. Thus, an effective layout practice to prevent process antenna violation is to stay within the antenna ratio design rule of the respective technology. Some general guidelines are,
1)Minimize the use of poly for routing
2)Minimize the use of poly to connect the gates together
3)Do not place contact and via directly on top of the transistor’s gate.
4)Avoid routing over the gates of critical transistors
5)Avoid routing over active areas of critical transistors.
(6) Contacts and Vias:
A high percentage of IC manufacturing defects is related to faulty contact and via. Instead of using single contacts or vias, using at least double contacts or double vias whenever possible reduces the possibility of defects.
(7) Metal coverage of contacts and vias:
Additional metal coverage on the contacts and the vias should be done if they are located at the end of the metal. A larger metal coverage reduce contact or via resistance variation and also reduce the chance of an open contact or open via.
(8) Spacing from poly to diffusion:
The performance of the circuit can be degraded due to an increase in the capacitive coupling between the poly and the diffusion, and a change in the length and width of the transistor. So the spacing from poly to diffusion should be according to the technology rules.
(9) Reduction of disturbances:
Analog design performances are sensitive to electrical disturbance. Disturbance in the substrate should be minimized as much as possible.
Two common types of substrate disturbance are
- Disturbance from minority carrier
Minority carriers are injected into the substrate from the source diffusions and the drain diffusions when the source potential or the drain potential of NMOS is below the substrate potential or the source potential or the drain potential of PMOS is above the N-well potential.
The drifting of the minority creates a potential difference or triggers a latch-up.
To reduce disturbances from minority carrier, guard ring around noisy transistors can be used. Guard ring considerations are as following,
(i) NMOS in the p-substrate with should be surrounded by N-well guard ring. N-well guard ring should be tied to VDD. The N-diffusions from the NMOS could inject stray electrons into the substrate. These stray electrons could be collected efficiently by the N-well guard ring that is biased to VDD to attract the electrons.
(ii) PMOS in the N-well should be surrounded with P-diffusion guard ring.
P-diffusion guard ring should be tied to ground. P-diffusions from the
PMOS inject stray holes into the N-well. These stray holes could be
collected efficiently by the P-diffusion guard ring that is biased to ground to attract the holes.
Ideally, the guard rings should be placed as closely to the likely noise sources as possible. The guard rings are also placed around the critical transistors to minimize stray electrons and stray holes from affecting the critical transistors.
Substrate coupling noise
To reduce substrate coupling noise, the guard ring may be used in the following configuration around critical transistors.
(i) Surround NMOS in the p-substrate with p-tap guard ring that is connected to ground.
(ii) Surround PMOS in the N-well with n-tap guard ring that is connected to VDD.
An important layout practice is to ensure that there is no (or very little) current flowing through any part of the guard ring. There are some disadvantages of the guard rings like, guard rings take up a lot of area and they also add capacitive load to the transistor. So, if the area in the design is of utmost importance, then guard rings should be avoided.
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